This invention relates to an encrypting device for use either in transmitting or recording a digital signal, such as a PCM signal, with each digit encrypted. This invention relates also to a decrypting device for use in combination with the encrypting device.
It is possible to provide an excellent encrypting and decrypting system by the use of algorithms released, Jan. 15, 1977 as FIPS PUB (Federal Information Processing Standards Publication) 46 by the National Bureau of Standards of the United States Department of Commerce (hereafter called the DES algorithm). Sixteen iterations of a calculation are, however, necessary on encrypting sixty-four-bit input data into sixty-four-bit encrypted data with the iterations preceded by an initial permutation and followed by the inverse of the initial permutation. The encrypted data are therefore obtained with an appreciable delay. In addition, synchronism must be kept for the sixty-four bits.
An encrypting and decrypting system revealed in U.S. Pat. No. 4,172,213 issued to Vera L. Barnes et al, assignors to Burroughs Corporation, makes use of a DES chip, namely, a chip for the DES algorithm. Consequently, the system according to Barnes et al is not devoid of the inconveniences inherent to the DES algorithm.
It is possible to provide an encrypting and decrypting system by resorting to the scrambling and descrambling technique, in which a maximal-length sequence generator is used. An example is disclosed in an article contributed by J. E. Savage to "The Bell System Technical Journal," Vol. XLVI, No. 2 (February 1969), pages 449-487, under the title of "Some Simple Self-Synchronizing Digital Data Scramblers." Only a few number of keys are, however, available for encryption and decryption. Furthermore, deciphering is possible even for an unauthorized recipient by analyzing a relatively small number of encrypted bits, such as 2m bits, where m represents the number of stages of a shift register used in the maximal-length sequence generator.